Issue link: https://iconnect007.uberflip.com/i/1526666
22 PCB007 MAGAZINE I SEPTEMBER 2024 Technical Needs, Gaps, and Challenges: High-speed PCBs Examples of the technology issues surround- ing high-speed PCBs, the associated needs, technology status of those needs, and gaps and challenges to overcome are highlighted in the tables in this article. e time period con- sidered is from 2023 to 2033. ese tables are excerpted from a more detailed table available in the online iNEMI roadmap. 2 Definitions for "Gap," "Challenge," and "Cur- rent Technology Status:" Technology Status Legend: For each need identified in the tables, the status of today's technology is indicated by label and color as follows: Faster Performance characteristics of dielectric materials used in stackups will evolve to man- age higher speeds and data rates. e manifes- tation of those refinements will also impact design and process improvements in thicker multilayer boards. is includes, but is not restricted to, higher layer counts, thinner dielectrics, tighter line width control, better registration, implementation of smoother cop- per, and alternative oxide process—all to limit losses that occur with higher frequency com- ponents in faster signaling. High-speed PCBs e roadmap's examination of high-speed PCBs focuses on solutions for high-speed dig- ital applications such as high-performance computing in data centers. In this context, rapid edge rates, as encountered in signal rise time or fall time (whichever is less), define the signal as "high speed." A rise or fall time of 1 ns implies a total signal bandwidth of 1 GHz or more, even with much lower switching speeds. Technology evolution is driven by require- ments to be: • Faster: Interconnect speed will oen be the limiting factor, particularly at the pack- age level. Per-lane signaling speeds need to continually increase and that implies extra signal bandwidths. Issues such as losses and signal integrity will be critical. • Smaller: Increased miniaturization in the core compute processing units leads to finer features and increased functional- ity and/or capacity on a given PCB, which leads to higher layer counts, as well as a reduction in all geometries. • Hotter: Even with improvements in energy efficiency, heavier computing workloads from paradigms like machine learning and increased overall capacity will drive up power consumption. PCBs will have to accommodate higher power delivery and new approaches to thermal management, such as immersion cooling for data centers. • Greener: PCB technology must become more sustainable, with the development of more energy-efficient manufacturing processes and with new materials and stackups supporting increased recycling and reuse. • Cheaper: For infrastructure electronics, "cost" must include more than the bill of materials; it must focus on the full lifecycle. Improved reliability is a major objective to drive down lifetime costs.