Issue link: https://iconnect007.uberflip.com/i/1526666
SEPTEMBER 2024 I PCB007 MAGAZINE 55 technologies where the cost per bit is critical. Facebook, Microso, and Google will not go 100% ceramic with their packaging; it's just too expensive. ey will go to the most cost- effective hybrids using glass/ceramic where it makes the most sense. PCBs and large panel substrates are also moving that way. LaRont: How can this realistically be addressed? ere are two ways to approach this packaging question: monolithic or motherboard fanout and off-the-board interposers and modules. Looking at an interposer off-the-board moth- erboard compared to a monolithic surface- mounted packaging routed board from a West- ern customer that is a 56-layer board, you'd probably say, "Anyone can build this board; it's 26 layers, and half of it is 2-ounce copper. e rest is wide traces used primarily for power distribution. All the data processing here is just between these nets. You've got a package here, and then the packages mount on over here, and there's a small amount of routing between them." But most of the data set processing is done between these nets. It is the same thing with PCIes (peripheral component intercon- nect express). You have the horizontal and ver- tical connections for that package. In 2026, I see alternate types of connectors, but verti- cal and horizontal will remain the dominant means for processing. Monolithic routing may still be the dominant design solution, but it's quickly being modified. LaRont: Wus is answering those packaging challenges with large panel processing? We are developing both strategies for the moth- erboard or baseboard at Wus. We have created a specific process called additive carrier pro- cessing for solutions of very large boards and very tight impedance needs for 224G+. Our large panels are 21x27 or 24x27. Producing interposers and modules of this size panel is much more cost-effective than traditional sub- strate processing. We're developing designs with multiple levels of interposers before you reach the actual motherboard PCB. Our fully additive circuit carrier approach eliminates the need for some of that as it has higher capa- bility for imaging than subtractive methods. It bridges the processing gap between previ- Figure 2: Monolithic routing. (Source: Nvidia)