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14 I-CONNECT007 MAGAZINE I JUNE 2026 cent layer above and below exclusively through laser-drilled microvias. Every layer is a potential routing layer. Pads only occupy the layers where the net actually needs to be. The via stub disappears, and the annular ring footprint shrinks. The result is a board that can support the escape routing demands of the most aggressive sub-100-micron pitch BGAs and advanced packaging formats without sacri- ficing layers to plumbing that was never needed in the first place. What's driving this? Semiconductor packages are shrinking their pitch while increasing I/O count. SoCs, advanced memory stacks, and RF front-end modules are pushing designers into territory where traditional HDI construction cannot provide enough routing channels in the available space. Board thickness envelopes are also tightening in wear- ables, implantables, and aerospace avionics. Every millimeter of Z-axis matters and ELIC addresses all of these simultaneously. At ASC, we have been building HDI boards for over a decade and have expanded into UHDI fabrication with the SAP and thin-foil processes, enabling sub-25-micron line and space capability. What we see clearly from the fabricator's seat is that ELIC is not simply an upgrade to HDI. It is a different manufacturing philosophy, much closer in process complexity to semiconductor packaging than to traditional multilayer PCB fabrication. That distinc- tion shapes every conversation about design intent, material selection, registration tolerance, and yield. These are the variables that ultimately determine whether an ELIC program succeeds or struggles. How Dense Can You Feasibly Get With ELIC? The theoretical density ceiling for ELIC means that by eliminating the through-hole barrel and connect- ing every layer through microvias, designers can route signals through a much smaller pad footprint and recover routing channels that would otherwise be blocked. In practical terms, a well-executed ELIC stackup can support line-and-space geometries down to 25 microns in HDI territory, and sub-25 mi- crons when combined with semi-additive process- es like mSAP or SAP. Counts that would require 20 or more layers in a Table 1: Understanding this gap is foundational to ELIC design. Minimum capability is a process boundary. DESIGN CAPABILITY PRODUCTION REALITY Minimum geometry limits Yield variability across production panels Ideal material behavior Material variation and CTE effects across cycles Perfect layer-to-layer alignment Registration tolerance that compounds with each cycle Single successful build Statistical process spread across volume production What is ELIC? Every layer interconnect (ELIC) is a PCB fabrica- tion architecture in which every layer connects exclusively to adjacent layers through laser- drilled microvias, eliminating mechanical through-holes as the primary vertical inter- connect. Unlike traditional HDI constructions such as 2-4-2 or 3-2-3, where through-holes serve a rigid core and microvias only connect build-up layers, ELIC makes every layer a fully usable routing layer. The result is higher rout- ing density, smaller pad footprints, fewer total layers, and elimination of via stubs, at the cost of significantly greater fabrication complexity and process discipline.