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ing over many cycles. While the properties of the copper plating in microvias will interact with the di- electric materials, excessive mismatches in thermal expansion between copper and dielectric can re- sult in the defects shown in Figure 2. Staggered microvias can distribute stress across capture pads and the surrounding dielectric, reducing the localized strains. In stacked microvias, stresses accumulate along the vertical column. A single microvia may tolerate mismatch, but multiple levels amplify strain at joints and copper fill interfaces. Rough hole walls after via formation and glass-rich vs. resin-rich areas of the dielectric can also concentrate stresses in localized areas within the via (as shown in the barrel crack in Figure 2). In an ideal world, there would be one material to recommend across various designs. But as engi- neers and businesspeople, we want to select the most cost-effective material that meets the reli- ability requirements of various designs and appli- cations. For high reliability in "many-layer" stacked microvia designs: While beyond the scope of this article, finite element analysis (FEA) of specific designs can be very helpful, as long as the properties for the actual materials used are known. I-CONNECT007 Ed Kelley is vice president, materials technology, at Victory Giant Technology (Huizhou) Co. Ltd. JUNE 2026 I I-CONNECT007 MAGAZINE 23 Select materials with very low Z-axis thermal expansion in temperature ranges of interest. In practice, this is achieved by combining a high Tg with very low pre- and post-Tg CTE values. Note that selecting a material with a Tg above the expected operating temperature means that the pre-Tg CTE will be the most important prop- erty for long-term reliability. But given that as- sembly process temperatures typically exceed material Tgs, selecting materials with high Tgs, which delays the onset of rapid post-Tg CTE, is also beneficial. This helps prevent via damage during assembly that can also compromise long- term reliability. Understand how modulus values impact perfor- mance. High-modulus materials maintain dimen- sional stability and resist warpage, which is ben- eficial for flatness in multilayer builds, but they transfer more stress to microvias, increasing the risk of cracking. When multiple build-up layers are used (and therefore multiple lamination cycles), it is also important to understand whether the material properties change as they are exposed to these thermal cycles. While most high-performance materials will not exhibit significant changes in properties, some materials will exhibit slight increases in modulus vs. thermal cycle, for ex- ample. Most material suppliers should be able to provide this data. In glass-reinforced microvia dielectric layers, use of spread-glass fabrics can improve the distribu- tion of the glass filaments within the dielectric, minimizing stress concentration due to glass- rich areas vs. resin-rich areas, as the glass will have a much lower CTE than the resin. In addi- tion, spread-glass fabrics can improve the qual- ity of the via wall. There are an increasing number of non-glass re- inforced materials available for microvia build-up layers. By removing the glass fabric, more uni- form via walls can be achieved and the stress concentrations caused by inhomogeneity of resin and glass in the dielectric can be eliminat- ed. On the other hand, make sure that this does not lead to increases in CTEs that offset the ben- efit. The non-glass-reinforced material needs to be very low in CTE. Lower-modulus dielectrics provide compliance, absorbing some Z-expansion and reducing peak stresses at via interfaces. This can enhance reli- ability in complex designs. However, excessively low modulus may worsen warpage or reduce overall board rigidity. In PCB designs using a multilayer sub-PCB with many microvia layers added, one approach, when possible, is to use higher-modulus materials in the sub-PCB to provide rigidity and resistance to warping, and lower-modulus materials in the build-up layers, as long as those build-up layers also have low CTE values. Tips for High Reliability in "Many-layer" Stacked Microvia Designs