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94 I-CONNECT007 MAGAZINE I JUNE 2026 related discrete components onto a common sub- strate or interposer platform to provide interconnect. The MCM wire-bond assembly sequence begins with die-attach, the placement of the die onto an ad- hesive deposited on the substrate's surface, with the active surface of the die facing up. Wire-bond pro- cessing follows, connecting the terminal sites on the die element to land pattern features located on the substrate's surface. Following wire-bond, the die and wire are coated with a liquid polymer material that, when cured, protects the die and delicate wire inter- connects from physical disturbance. The wire-bond process uses extremely fine-diam- eter wires (< 40 microns or 0.0015"), typically made of soft metals such as gold, silver, or aluminum. The classic MCM variations are assembled onto a metallized, ceramic-based substrate (Figure 1), a dielectric material that closely matches the CTE of the silicon die elements and exhibits excellent thermal conductivity. Other variations may use glass-reinforced FR-4 or polyimide dielectrics as a base platform. The fabrication processes for these materials enable multiple-layer construction and, when employing a semi-additive copper plating process, very high interconnect density at a moderate fabrication cost. Flip-chip Packaging As an alternative to wire-bond processing, many companies opted to adopt a process to terminate the die in a face-down orientation known as flip-chip. The face-down process was originally introduced commercially by IBM in the 1960s, using high-lead solder to form a raised terminal at each wire-bond site. The original IBM concept employed very small diameter solder-coated copper spheres placed on the lands originally furnished for wire-bond process- ing. In 1969, IBM replaced the copper-core spheres with solder-alloy bumps, as shown in Figure 2. The solder material proved to be more econom- ical, easy to deposit, and compatible with the SMT assembly process: 1. Print or deposit solder paste onto the land pattern. 2. Place components. 3. Employ a heating system to melt the solder to enable the joining of the component termi- nals to their respective land patterns on the substrate. As the molten alloy begins to cool during the joining process, the alloy bumps collapse slightly, reducing the standoff height between the die and substrate surface. For the initial solder-bumped die process, IBM adopted C4 (Controlled Collapse Chip Connection) technology. The increased component density enabled by multiple uncased die elements on a single inter- poser can significantly reduce the complexity of the host PCB. Close coupling between active devices will minimize power consumption and improve func- tional performance. It's not uncommon to include discrete passive components (resistors and capaci- tors) on the same surface using the reflow solder processing for termination noted above. In flip-chip packaging, the smallest possible package is always the size of the chip itself. As the industry moved more toward miniaturizing semiconductor packaging in the mid-1990s, stan- dards for chip-size and chip-scale packaging (CSP) began to evolve. Among the categories defined were fine-pitch BGA, die-size BGA, and wafer-level BGA (WLBGA), in which terminal forming occurs while die elements remain in wafer format. Fan-in Wafer Level Packaging The WLBGA is a type of BGA in which the finished component's outline is the individual die element. Terminal features required for attaching the semi- conductor to a package substrate or circuit board Figure 2: 0.5 mm terminal pitch, flip-chip configured LMC555 CMOS Timer. (Source: Texas Instruments) D ES I G N E R 'S N OT E B O O K