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JUNE 2026 I I-CONNECT007 MAGAZINE 97 die-to-die interface, the primary I/O channels and power and ground terminals are located on the bottom surface of the interposer. Furthermore, separating the pre-tested chiplet support functions from the core processor has improved process efficiency and maximized overall end-product yields; however, the shrinking of terminal size and pitch has become extreme. As the terminal features become narrower, solder process defects increase: opens, shorts, and bridging. Ideally, traditional solder processing can be avoided. Hybrid Bonding Hybrid bonding is a heterogeneous or homoge- neous direct-bond interconnect technology that enables vertical joining of very fine-pitch semicon- ductor die-on-die, die-on-wafer, and even wafer-on- wafer without the use of solder or other additive con- ductive materials between the attached die surfaces. This technology is increasingly used to vertically join a wide range of semiconductor devices, including sensors, memory, and logic die elements. Contrary to all traditional packaging technologies, where the interconnects are joined first, then an underfill is in- serted to occupy the space between the intercon- nects, the direct bond interconnect1 process (hybrid interconnect) does not use solder or flux and does not require underfill between opposing surfaces. Die bond interconnect is an enabling low-temper- ature, low profile die-to-wafer and die-to-die hybrid bonding technology platform. By eliminating the need for copper pillars and underfill, the process enables a dramatically thinner stack as compared to conven- tional approaches, allowing the stacking of die that are the same or different sizes, processed on fine or coarse wafer process technology nodes, or manufactured on the same or different wafer sizes while readily scaling down to 1 µm inter- connect pitch. The opposing copper terminal surfaces are first aligned to one another and brought together. Alignment for this unique joining process is critical. The developer has stated that the current alignment accuracy of flip-chip bonders is in the 1–10 μm range. Interconnection is completed using a moderate batch anneal, where the Cu bond pads expand to form a homogeneous metallic interconnect with grain growth across the bond interface. The chemical bond between oxides is significantly strengthened, ensuring high reliability. Note: From a historical perspective, integration of multiple functional elements onto a single monolithic platform has become commonplace, although they prove most practical for high-volume applications. Monolithic integrated circuits are electronic circuits that consist of transistors, resistors, and diodes, and their connections, formed on the surface of a single piece of silicon, resulting in a seamless system-level structure. Developing these ASIC products often requires a great deal of engineering resources, monetary commitment, and time. Although many hybrid circuits can be replicated and produced as monolithic integrated circuits, it may not be economi- cally feasible unless large quantities are required in the long term. I-CONNECT007 References 1. In 2015, Tessera Technologies, an Adeia member company in Santa Clara, California, acquired Ziptronix and added the oxide-bond process to its DBI IP portfolio. Vern Solberg is an indepen- dent technical consultant, specializing in SMT and microelectronics design and manufacturing tech- nology. He is the author of several books, including Design Guidelines for Surface Mount and Microelectronic Technology. To read past columns, click here. Figure 4: Intel's fourth- generation Xeon processor. (Source: Intel Corporation) D ES I G N E R 'S N OT E B O O K