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JULY 2023 I DESIGN007 MAGAZINE 43 variation is the interposer-substrate, the sili- con or glass-based platform that glues every- thing together (Figure 2). Circuit interconnect and land pattern geom- etry for the processors and chiplet elements are defined in millimeters and micro-meters (or microns), significantly smaller than the traditional surface mount configured circuit board; CAD tools to support interposer devel- opment are already in place. Although silicon wafers or glass panels will be the preferred base platform for the highest density applications, there are inorganic mate- rials that will accommodate the merging of chiplet die elements with a more relaxed den- sity. In any case, it's simply a matter of scaling. Status of Standards for Chiplet Elements e industry chiplet standards are still being ironed out, but there are two major proponents: the Universal Chiplet Intercon- nect Express (UCIe) Consortium and the Joint Electronic Device Engineering Council ( JEDEC). Activities within the JEDEC JC-11 subcommittee's scope include all aspects of the mechanical design, integration, interoper- ability, and standardization of all semiconduc- tor devices. e organization's responsibilities include generating design guidelines, stan- dardized measuring methods for mechanical features, and mechanical outlines for com- mercial microelectronic packages and assem- blies. e member-supported working groups also develop mechanical, environmental, and ergonomic performance specifications, rec- ommend land pattern geometry, and establish the designators for identifying semiconductor device packages. While several semiconductor developers have already established their own proce- dures for integrating their proprietary chiplet families, JEDEC member companies have initially targeted standards development for high-capacity memory, standards for stacked DRAM, as well as open compute platform (OCP) as part of their open domain-specific architecture initiative. ese standards will guide the chiplet builders in developing an elec- tronically standardized chiplet part descrip- tion to make it easier to create a chiplet-config- ured system-in-package (SiP) design. By using chiplets, the ultimate goal is to reduce product development times and eliminate wafer pro- cess deficiencies by integrating pre-developed and electrically certified (KGD) dies onto an interposer. Chiplet standards development activity is well underway, although the idea of a LEGOS brick format, with the same size die and a uni- versal terminal pattern for interface (that some Figure 2: Multicore CPU with memory chiplet set on a silicon interposer.