Issue link: https://iconnect007.uberflip.com/i/1526666
56 PCB007 MAGAZINE I SEPTEMBER 2024 ous substrate technologies and advanced PCB technology. Now, RDL layering can be done where the SI best fits and lower the number of very advanced substrate layers. Advanced sub- strate layers are significantly more expensive. It is a significant challenge to subtractively build these large panel baseboards cost-effectively with six HDI lamination cycles. At Wus, we went back to the drawing board and said, "If you have typical subtractive HDI buildup (like mSAP or SAP), you're build- ing these laminations up, and you're not able to inspect them; they are part of the board." is is a cumulative yield problem. e larger the pieces on a panel, the greater this impacts the BOM cost. Imagine a board being six HDI laminations and 24 layers in the subpanel, plus two up on a 21x24 board panel. If you have one open on one layer internally on one board, that's a 50% increase in your BOM cost. is is not realistic for scaling to very high volumes. It's very challenging to achieve impedance val- ues with subtractive below 7%; 5% will soon be standard and additive circuits can be modi- fied very easily as the CAD data to trace width are the same. Now we have semi-additive and fully additive capability and can use it when it's best for the application and additional needs, like ultra-low CTE BGAs. We needed to develop a process that would allow us to build the traces offline, inspect them, and make sure they are fully functional before we laminate. Only then will we laser through and make connections layer to layer. is pro- cess is very reliable. We have a very high CpK for via connections, but the RDL routing for mSAP and SAP can be lower. It's a hidden secret with subtractive processing that you build in fail- ures. at's why the processes are becoming so advanced: to have a better guarantee of qual- ity as you build—but with that comes a very high price. For 50/50 µm lines and spaces, you shouldn't have to build it in a $1 billion factory for medium volume. It should be for the lesser number of advanced substrate layers for fan- ning out the pitch from the die. We call this pro- cess "additive circuitry carrier processing" or "known good layers." It's part of the large sub- strate/PCB motherboard roadmap. I don't see how we'll get away from it without mSAP or SAP processes and materials well beyond the required capability to form these layers. Barry Matties: Is "known good layer" some- thing being widely adopted by fabricators? "Known good layer" is borrowed from "known good die," because dies were so expensive. Dies are very small, and there were so many on a sin- gle disc that they would test the dies, remove the ones that were defective, and replace them with good ones, providing final fabrication assurance of "known good die." Cost impact to yield was minimized by completing only the full disc volume through future processing. Wus' method with known good layer buildup and cores is the same logic. Looking at it from a PCB large panel processing standpoint, it's important to know the signals are good before you put them on the board. With material so much more expensive, future manufacturing where neither of these are examined will start at a huge cost disadvantage. Figure 3: PCB interposer aka XPU accelerate module card, OAM, etc.