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66 PCB007 MAGAZINE I JUNE 2025 tent allows etchant to enter the via and dis- solve copper. Since puncturing both tent sides is rare, copper tends to erode from one end, resulting in an asymmetrical void taper- ing toward the broken tent. In extreme cases, all copper may be removed. See Figure 4. Direct Metallization Process Voids Direct metallization eliminates the tradi- tional electroless step, using palladium, car- bon/graphite, or conductive polymer coat- ings. Voids may result from insufficient cat- alyst or polymer deposition, particularly due to inadequate hole wall conditioning. Brushing panels aer carbon deposition can remove catalyst near hole rims, prevent- ing plating continuity. Pumicing aer depo- sition can dislodge particles. While graphite processes tolerate brushing better, both pro- cesses require careful handling. Voids Due to Copper Removal Even aer successful copper deposition, copper can be lost due to: • Moisture in holes leading to oxidation • Aggressive microetching • Blistering or flaking of deposits • Excessive brushing during surface prep "Ring voids" occur when copper is brushed off around the hole rim. ese appear as crescent-shaped gaps, oen matching the machine direction of brushing. An unusual defect is the "corner void," where copper is missing from all four via corners. is may be caused by thin deposits at high-current-den- sity areas due to overuse of levelling agents. Reducing paddle agitation or leveller con- centration can alleviate the issue. Conclusion Hole voids in PCBs can result from a wide array of process issues, starting from drilling and extending through plating. Each void's location and shape can provide critical clues about its origin. Since multiple interacting fac- tors oen contribute to void formation, a thor- ough, step-by-step process review is essential to identify and resolve these defects. PCB007 Resources • "Tech Talks #114–#117," by Dr. Karl Dietz, March- June 1995. • "Desmear—The Key Processes for Reliable Through-plating of Printed Circuitry," by A. Ang- stenberger, Circuit World, Vol. 20, No. 4, 1994. • "Plated Through-hole Processing: An Integrated Approach," by Mike Carano, Plating and Surface Finishing, August 1994. • "Process Control of Electroless Plating," by Mike Carano, Proceedings, FabCon, May 1994. • "Through-Hole Coverage Keys," by W. T. Eveleth et al., Circuits Manufacturing, December 1986. • "Plating Blockout During Gold Electroplating of Hybrid Microwave Integrated Circuits," by J. Rea- gan & O. Qutub, Plating and Surface Finishing, January 1991. • "Reducing Plating Voids," by M. Lefebvre, PC Fab, Vol. 16, No. 4, April 1993. • "The Chemistry of Plating Small Diameter Holes," by J. J. D'Ambrisi et al., PC Fab, April 1989. • "Preventing Resist Related Through-hole Voids," by G. S. Cox & W. L. Wilson, Technical Bulletin TB-9527, DuPont Electronics. • "Review of 'Direct Plate' Processes," by Karl H. Dietz, AESF SUR/FIN '95, Baltimore, June 1995. • "Antipitting-Zusaetze fuer galvanische Electro- lyte," by V. Mirtschewa, Galvanotechnik, 1991. • "Reducing Copper Plating Pits in PWBs," by R. A. Olson, August 1991. • "A Farewell to Pitting," by M. Jani & P. Diehl, PC Fab, Vol. 16, No. 3, March 1993. Happy Holden has worked in printed circuit technology since 1970 with Hewlett- Packard, NanYa Westwood, Merix, Foxconn, and Gen- tex. He is currently a con- tributing technical editor with I-Connect007, and the author of Automation and Advanced Procedures in PCB Fabrication, and 24 Essential Skills for Engi- neers. To read past columns, click here.