IPC International Community magazine an association member publication
Issue link: https://iconnect007.uberflip.com/i/1545404
16 I-CONNECT007 MAGAZINE I JUNE 2026 Unlike HDI, which builds outward from a pre-drilled core, ELIC begins at the center with a core pair— L1 and L2—and adds one new layer to the top and one to the bottom with each sequential lamination cycle. This means registration errors do not simply accumulate from one end of the build to the other; they propagate symmetrically outward, and the out- ermost layers carry the greatest total positional un- certainty from the full history of the build. A positional shift of ±10–15 µm may be inconse- quential on a forgiving HDI structure. On a UHDI design built around 50–75 µm microvias and reduced capture pads, that same shift can mate- rially reduce the usable landing margin. In a six- cycle ELIC build, a registration error introduced in Cycle 2 persists in the final outer layers. It is never corrected, only added to. The designs that survive this are the ones that account for realistic process window behavior, not ideal alignment. We have addressed this by investing significantly in imaging and lamination registration systems, specifically because ELIC tolerates less drift than any prior construction we have built. Process control around panel expansion coefficients, tooling Figure 3: A 15 µm registration shift reduces capture pad annular ring from 25 µm to 10 µm, substantially increasing breakout risk. In ELIC, this condition exists at every level of the stack and compounds with each cycle. systems, and material conditioning before lamina- tion matters equally: these are process disciplines, not equipment specifications. Common registration-driven failure modes in ELIC include partial microvia capture, microvia breakout, stacked via misalignment accumulating through successive layers, solder mask encroachment onto exposed pads, insufficient mask dams leading to bridging risk, and trace exposure from shifted outer-layer relationships. None of these is a random event. They are predictable consequences of insuf- ficient design margin in the presence of normal process variability. Lamination Cycles and Cumulative Thermal Stress Every sequential build-up cycle adds thermal ex- posure to the materials already built. This is man- ageable in a two-cycle HDI board. In ELIC with six, eight, or more sequential lamination events, each cycle exposes prior copper and dielectric to tem- peratures and pressures that induce stress and di- mensional change. Materials must be specifically qualified for repeated thermal cycling without de-