IPC International Community magazine an association member publication
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JUNE 2026 I I-CONNECT007 MAGAZINE 17 lamination, Z-axis expansion, or degradation of dielectric properties. Not all materials that perform well in a two-cycle HDI build will hold up in a six- cycle ELIC build. The materials that meet the required criteria—thin build-up films, select resin-coated foils with high dimensional stability and good laser drill response—are not commodity items. They are sourced from a limited set of suppliers, and material avail- ability for qualified high-cycle laminates is a genuine operational constraint for North American fabricators. Via Reliability: The Risk That Compounds With Every Layer The PCB industry has been working through stacked microvia reliability issues for over a de- cade. IPC white paper IPC-WP-023, "Performance- Based Printed Board OEM Acceptance—Via Chain Continuity Reflow Test: The Hidden Reliability Threat," documented field failures in HDI boards with stacked vias, traced to incomplete copper fill and electroplating conditions that created a weak interface at the microvia-to-target-pad junction. In ELIC, this problem multiplies with every additional stack level. The most critical process control point in ELIC is copper fill quality at each microvia level before the next build-up layer is applied. An incompletely filled microvia creates a void, which becomes a stress concentration point under thermal cycling. In a two- level stack, a void may be caught by cross-section inspection. In a six-level stack, a void three layers deep may not be detectable by standard AOI and may only reveal itself after assembly or in the field. Our process for ELIC at ASC requires 100% cross- section sampling at defined build intervals and electroplating chemistry management that is signifi- cantly tighter than what we apply to standard HDI builds. This is non-negotiable for production yield and reliability. Material Cost and Cycle Time ELIC builds differently from a cost and throughput standpoint. The unit cost of specialty dielectric lay- ers is higher than commodity laminates. The lami- nation cycle count is higher. Per-panel throughput is lower because each sequential cycle requires the panel to move through imaging, laser drill, desmear, plating, and inspection before returning for the next cycle. Build time is measured in days per sequential cycle, not per board. Customers accustomed to standard HDI lead times are often surprised by ELIC cycle time. For applications requiring short-turn prototypes, ELIC requires early commitment to a fabricator with dedi- cated capacity and the process infrastructure to support rapid sequential cycling without sacrificing process control at each step. I-CONNECT007 Anaya Vardya is president and CEO of American Standard Circuits; co-author of The Printed Circuit Designer's Guide to… Funda- mentals of RF/Microwave PCBs and Flex and Rigid- Flex Fundamentals. He is the author of Thermal Management: A Fabri- cator's Perspective, The Printed Circuit Designer's Guide to DFM Essen- tials, and The Companion Guide to Flex and Rigid-Flex Fundamentals. Visit I-007eBooks.com to download these and other free, educational titles. " ELIC is not simply an upgrade to HDI. It is a different manufacturing philosophy, much closer in process complexity to semiconductor packaging."