Design007 Magazine

Design007-Jun2024

Issue link: https://iconnect007.uberflip.com/i/1522071

Contents of this Issue

Navigation

Page 31 of 75

32 DESIGN007 MAGAZINE I JUNE 2024 dynamic range of the receiver, eats into the noise budget, and can cause false triggering. As signal rise times become faster, consider- ation should be given to the propagation time and reflections of a routed trace. If the propa- gation time and reflection from source to load are longer than the edge transition time, an electrically long trace will exist. If the trans- mission line is short, reflections still occur but they will be overwhelmed by the rising or falling edge and may not pose a problem. But even if the trace is short, termination may still be required if the load is capacitive or highly inductive to prevent ringing. Generally, when the trace length exceeds one-sixth of the elec- trical length of the rising edge rate, then termi- nation is required. We typically dampen reflections in high- speed PCB design by using resistive termina- tions (series or parallel) to match the imped- ance of the line to the driver. However, I have also seen the reflections caused by using a driver strength that is too high for the load. Driver strengths typically range from 4 mA to 16 mA. A 16 mA driver is generally required for multiple loads—for instance, a DDR4 signal driving multiple SODIMM memory cards. In this case, the transmission lines are longer and the capacitive load higher, so simulation is nec- essary to confirm the required driver's current strength. To dampen the signal, terminations are typically placed on the memory card itself. However, if the signal is delivered to only one or two onboard memory devices, then the sig- nal strength can usually be reduced to a mini- mum of 8 mA to prevent reflections. With the driver strength set correctly, we need to determine if there is a mismatch of imped- ance. But how do you know the impedance of the driver and the transmission line? First, an accurate field solver is required to determine the impedance of the PCB traces (Figure 2). Figure 2: iCD Stackup Planner simulates the trace impedance.

Articles in this issue

Archives of this issue

view archives of Design007 Magazine - Design007-Jun2024