Issue link: https://iconnect007.uberflip.com/i/1522641
JUNE 2024 I PCB007 MAGAZINE 85 Let's Dig Into Some Data Overall, impedance measurements across all 58 panels follow a normal distribution but are centred around 82.25Ω which is skewed almost to the bottom of the 88Ω nominal ± 8% toler- ance of 80.96Ω-95.04Ω. So, the impedance is consistently low, and clearly, they need to tweak the recipe, but is there anything else we can glean from this wealth of data? e highest yield panel is at 94% with five failing PCBs; not a single panel in the sample passed every PCB. is is getting interesting, as there are some obvious high and low impedance spatial depen- dencies starting to show. What does this look like if normalised across all the panels? What can cause this irregular distribution of impedance? Is it as simple as uneven pressing forces across the panel? Table 1: IPC resolution of TDR systems Figure 3: With 6σ values clocking in at over 10Ω, they won't meet a ±8% tolerance. With that variation, it would be a struggle to maintain a 100Ω ±10% tolerance, even if it was distributed dead-on nominal. Figure 4: The heatmap is across all impedance mea- surements in the 58-panel sample. Unsurprisingly, the readings for a mostly passing panel are hot, meaning the values are at the high end of the ear- lier histogram. We don't have to go far to see the lowest yield. Panel 28 is the next in sequence and sits at the opposite end of the spectrum with a piti- ful 2.5% yield.